Sam Sivakumar of Intel talks about Lithography and Patterning: Part 1
[MUSIC]. Okay, good afternoon everybody. Can you, can you hear me? Hopefully. Okay. my name is Sam Sivakumar, I work at Intel, I, as [UNKNOWN]. And I started working there in 1990 after getting a double E degree from University of Illinois. so I’ve worked in lithography pretty much my entire career so I’ve got to see how the technology has evolved over the years. and hopefully I can touch on some of that stuff over the course of this talk. And I’ve got a pm flight out of town, so I’ll be around for awhile. So, if anybody wants to, you know, talk to me after the, after the presentation that’s fine.
Feel free to interrupt me if you have any questions, so So this is a very broad subject, so I based on the input I got from Aneesh. I am assuming that you have, you, you have some background or you’ve been the, as part of your class. You’ve had some exposure to the different lithographic techniques that are out there. so I am going to assume you know some of the basics at least some terms that that I’ll refer to. If you don’t, just raise your hand we’ll can go over it in a little bit more detail. Okay, so you know, Moore’s Law is this this statement that relates how how the semiconductor industry you know, is economically feasible. And it’s, it’s you know, dictates how, by doubling the number of transistors you can pack onto a chip every you know, year and half or a couple years, you’re able to maintain this dollar per transistor number you make it go down. And so your able to provide more capabilities to the, the end user to the customer. Right? So, so over the course of you know, the last 30 years or more you know, the dollar per transistor value has gone down.
And the reason that has happened is because you can pack more and more transistors on to a piece of silicon. so you know obviously in order to do that you have to be able to print things smaller and smaller, because you can’t simply make the chip bigger. The chip is roughly the same size over the course of those years. so lithography really is sort of the engine that drives Moore’s law. That, that enables us to make these feature sizes smaller and smaller.
and so you know, the economic benefit of course is that you’re able to provide much more capability in a cell phone today than you had in a supercomputer you know, 20 or 30 years ago. but of course the technical challenge goes up proportionally. It’s a lot, it’s really hard to make these features small. so, if you look at you know, the 22 nanometer technology is what is in the marketplace right now. I have it all the way at the right end of the page. 90 nanometers came out in 2003. and then every two years roughly, we’ve been trying to get a new process technology out in the market. so every one of these generations had some new innovation, either in the transistor or in the way you wire the transistors and so on. So, and of course, the features sizes gets smaller every generation. So, the 22 nano-meter, the last column there, that really represents the state of the art in the market place today.
And so we’re, we’re starting, we’re actually not starting. We’re working on 14 nanometers which is the next node after that, and there’s already some research going on in the 10 nanometer node which is the one beyond that. So fair amount of work that’s that is past that page, it will probably come out in the next 2 to 4 years. so if you look at these two plots, what I’ve shown here is a feature size over time, and on the right hand side is the, the area of an s trans cell, a basic memory as a function of time. And so there’s a log plot. So, basically, the, the featured sizes gets smaller by 0.7x every generation, every 2 years. You know, you try to shrink the future sizes by 30%, and so you’re area goes down by half every 2 years.
Alight, because it’s, if you square that. So, that really represents you know, how you’re able to pack more and more transistors on to a chip twice as many transistors every year. and you know, the, as you can see, the you know, the, the SRAM cell has evolved considerably over the course of you know, multiple process generations. So, there’s an interesting picture I like to show you know, in 1978, a, a contact, which is this you know. Again, if you raise your hand if you don’t know what a contact is. But a contact is a connection between two metal layers. It’s a vertical sort of connection. And so, that, that was a contact look like, and so you pack 10, 30 nanometer memory cells inside one single cell contact you know, from 1978. So, it just graphically illustrates you know, how, how much smaller features are now compared to they were you know, just a short time ago. So, you know, from a lithography stand point, you’re, in order to make things smaller, there are a lot of things that need to happen. Electrically your transistor has got to get smaller.
Your wires, you have to understand how the resistance and capacity of your wires change over, over process generations. But from the lithographer’s stand point, our goal, it, [COUGH] is to develop patterning solutions to continue this trend in the most cost-effective way possible. You know, and, and a cost is a recurring theme I’ll, I’ll harp upon over the course of my talk. but lithography is the most expensive process step in the fab. You know, right now, I, you know, estimates go from anywhere to 40 to 50% of the total cost of making a chip is lithography. You know? So, there’s a lot of effort that goes into trying to understand where all the money is going and figuring out how to do your lithography cheaper, in a less expensive, in a less expensive way. So you obviously want to keep the trend, you don’t want to slow that down. But at the same time ,you’re trying to understand how do you do it with you know, in the most cost effective way possible. Now the lithographer’s mission is not just to figure out technically how to make things smaller, but how to do it cheaply. Alright.
so before I jump into to some of the tech-, some of the details, I just have one slide that talks about you know, the, how conventional lithography is done. So this is a you know, a scanner, which uses optical lithography. You know it’s light that comes in, the green lines there. There’s a mask that has your feature. and the mask will diffract your light that comes in, so you have different diffracted orders.
You have the first order and the second order, and so on. So obviously the zeroth order which comes straight through has no spatial information in it. If you think about a Fourier series, the zeroth order has no spatial information. You have to capture at least the first order, the sinusoidal, you know. The first, the first order has to be captured by your lens in order to figure out you know, if you have, if you have a grading of lines and spaces on your mask, in order to capture the periodicity of the features you’re trying to print. You gotta capture at least the first order. So that kind of defines how big your lens needs to be. The lens literally has to be big enough to capture the first order. And, and so the relationship there on the right-hand side, you know, sine theta equals m lambda over d. What it says is that the angle of diffraction of your first order or, or higher order depending on which diffracted order we’re talking about. is obviously you know, a function of your wave length, and it’s inversely proportional to the size you are going to define.
So, the smaller the feature size, the, the more the detraction angle and so the bigger lens you need. So, one of the things that has happened over multiple process generations is your lenses have to get bigger and bigger and bigger to print smaller sizes. Right? and so that defines how complicated your scanner is. And so a huge amount of technical know how goes into making these giant lenses that have extremely low aberrations you know, very, very high quality. so there’s this equation known as [UNKNOWN] equation, you guys may have seen it. It’s part of your course. which relates your feature size you can define, it’s proportional to your wavelength. And it’s in mostly proportion to the numerical aperture of your lens. Which is varied to how big the lens is, right. so the bigger your lens, the smaller the feature size you can define. The lower the wavelength you use, the smaller the feature size you can define.
And the proportionality constant k1, it’s really a metric of how difficult your lithography is. Right? So, typically what you, you know, in, in, in, from a practical standpoint, if your going to have a factory that’s making these chips. The k1 needs to be about or so, not a whole lot smaller than 0.3. So, that kind of defines, what’s this you know, given a wavelength and numerical aperture, that defines how small a feature size you can practically define. You try to print features smaller than that, and you’re going to get a lousy process. It’s not going to do very well in a factory. So this plot here, I, I’ve shown here as half-pitch, which is you know, the featured size. You can roughly imagine if you’re printing equal lines and spaces.
So that’s on the x-axis. And then k1 is the proportionality constant on the y-axis. So I drew a line, a horizontal white line that says anything below that is, is no good for manufacturing. Anything above that’s okay. Right? And so these lines here, the red line, the blue line and the green line, that that’s running across the graph. Those represent basically k1 for a given set of lambda NA. So the first one is 0.8, the red one is NA, so NA is 0.85. And the lambda is argon fluoride, which is 109th nanometer illumination.
Right? So, those two numbers are fixed and you just plot basically k1 versus d. And what this says is that for this kind of lithography where you have a lens that’s NA, the size of the lens is NA and you’re using 109th nanometer illumination. You really can’t print features that are smaller than about 70 nanometers. Right? You, you’re not, it’s not going to do very well if you’re trying to run a factory. So, in order to do, go to smaller feature sizes, you’ve gotta jump up a little bit, maybe to 0.93NA. Right? So then that’s the next step. So these are actually the , the types of scanners that have been around on the market place 0.85NA, it’s kind of an old machine.
You know, we don’t even use it anymore. the 0.93NA machine is probably the the oldest machine that we practically use on the RF side. The next big step. So, if, if you look here In 2005, for the 65 nanometer node we used the NA machine. So the feature sizes were about 100 nanometers and it did pretty well. You know, we were right about this white line. When we moved to the 45 nanometer node, we, we were okay, we just. The NA to had just come out so we skipped we just moved onto that. When we ended 32, it was clear that had we stood on those old tools, we would have fallen below you know, the, the right here, we’d fallen below that white line. So we had to move up to NA, which is something called an immersion scanner. You know, we use water between the lens and the wafer to improve your resolution. So we jumped up there. And then what, 22 nanometers where it is still sort of right around so we managed to make this work with NA ArF. So, again, you know, if you want to reduce d, you know, you can gen the bigger lenses, you can reduce the wavelength or figure out a way to run at lower k1.
So this 0.3, can you challenge this number? Can you really try to run lower than that? So lots of tricks one can use, try to run as close as possible to the white line and maybe even below it. so those are the kinds of you know, development activities that we have to do to come up with a lithography operating point that can print the feature sizes we need. The problem we run into of course is that you know, on ArF, NA represents the highest numerical aperture you can practically make. You know, it, it’s a function of a lot of different things. It’s a function of the refractive index of the, of the water, the glass you use and so on. So there are ways to get around it, but they’re not very practical. So for all intensive purposes, NA is the, is the maximum NA possible. And what, and what you can see here is. This is the NA, so the numerical aperture has gone up from about to all the way up to 1.35.
There’s really no more room to go up. and at the same time you’ve been dropping your wave length from 436 to 365 to 248 to 193. So this combination now ,193 nanometer light with a NA vector represents the state of the art that’s as far as ArF lithography is going to go. So that kind of defines a floor for the feature sizes you can define below, which is simply not possible to use conventional ArF lithography. so the next big step is to find another wavelength. Right? So this, there’s UV, it’s the next big lithography node that’s out there. And, and that’s quite a big step in, in wavelength, you go to 13 and a half nanometers all the way from all the way from 193 nanometers.
So, so you get a lot of resolution. But along with that comes the huge you know, number of challenges. [UNKNOWN] lithography is horrendously complicated. And I will spend a lot of time talking about that. so EUV is really the main area of research and development focus right now in lithography out there. So the lithography scaling problem, going back to the um,, to the [UNKNOWN] equation is you know, to reduce D. I just am kind of repeating what I had in my previous slide. You could increase NA, but of course there you’ve got a problem because the maximum NA of you already hit. You can reduce the wavelength. The problem there is EUV, like I said is extremely complicated and it has been delayed. You know, we, we’re doing our best to get it into manufacturing, but it’s proving to be far more difficult than you know, anybody could have imagined.
so a lot of effort also is now going into figuring out how did you make ArF lithography work, you know? Are their tricks we can do in lithography you know, the, the source of the mask with the wafer, you know? I talk about things like pitch division. And then are there non-optical approaches? Multiple E beam direct light. I can use E beam lithography to, to pattern features. nano-imprint, directed self-assembly. There are all these other techniques that are are being investigated. A lot of these are pretty, in a pretty rudimentary state you know, as far as there, as far as as far as how soon you think you can get it into manufacturing.
So probably a few years to go to get those in a manufacurable state. So, I think one of the key things is your, your traditional scaling approach which has consistently been, make the lens bigger, drop the wavelength when you need to. You know, that, that’s run out of steam. So we really need to think about other things to continue scaling. So, what are the challenges in, in scaling feature size. when you think about you know, they, they all are equations and all are [UNKNOWN] lithography from a very theoretical standpoint. you think of equal lines and spaces, you think of printing a grating. You know, a lot of the analysis that are done, like the graphs I showed, talk about you know, printing lines and spaces. Which is great if all we have to do is print lines and spaces, then is makes lithography a whole lot easier.
Right? The problem is that a real layout looks like that. You have lines and spaces here and there, but you have all kind of other things. You have these end-to-end structures, you have these two ends that face each other. Very very difficult to pattern. You have different line widths, it’s not a constant grading from one end to the other. You have narrow lines, you have wide lines. You have routing that go both ways, some horizontal, some vertical. Right? And then you have all kinds of bends. You have all these weird features that don’t always want to pattern very well. So, gratings are really easy to scale, relatively easy to scale I should say. Real layouts are not, real layouts are really hard to scale. So, a lot of challenge really goes into figuring out how to manage lay, real layouts and make them suitable for, for scaling. Make them lithography friendly, so to speak.
Right. So the solution there, you know, it sounds simple is let’s make everything look like a grating. Right? So, this is what layouts used to look like at 65 nm. The real circuit you know, in a, in a microprocessor. And what we did going to 45 nanometers, so, is really try to figure out how to rearrange these transistors to make it look like that. So this is what a printed wafer looks like. These are gates, transistor gates. Here’s a, you can kind of see the isolation underneath. Each one of these, this is a transistor there, a transistor there. so it’s a lot more regular. a lot more like a grating. It’s not perfectly a grating, but it’s a whole lot better to pattern than this thing here. So it took a huge, it took a huge amount of effort, a huge amount of collaboration with our design groups and the fab, the lithography guys, to figure out. How do you make, how do you go from here to there without giving up density? You know, if, if you did that and then your chip got twice as big, that’s no good.
So you have to be able to do this kind of thing without sacrificing density. And so, it’s, it’s a mindset change in, in a lot of different ways for designers. For the tools that lay out circuits and for the lithography itself. but these [INAUDIBLE] may have made that happen, [INAUDIBLE] this is what circuits the states look like. and that’s the way they’re going to look like, because it’s a whole lot easier to pattern that than this.
So unit directional grided layouts are the way of the future. You know, once again, this is 65 nanometers. You can see here, this is diffusion. These are transistors, these are gates that go across. So each one of these is a transistor. And that’s what a cir, circuit looks like at 45 nanometers. Real uniform single pitch you do have the cuts. We have to figure out how to do that, but for the most part it looks a lot more like a grating than this thing. So, the goal in lithography now is try to figure out, how do you make a layout look, make a grating and then cut the grating.
Right? So you’ve got a grating and a cut. So the, the, the. A lot, a lot of effort that we are trying to do is working with the designers to figure out how do you take any circuit layout and turn it into something like this. Where you can lay it on a grating, which we know how to do reasonably well, and then figure out how to cut it, which is a little bit harder to do.
But at least you get rid of a lot of the problem layouts that some of the earlier technologies had. So, you know, from this point forward, I’ll talk about these two challenges here. You have, the first challenge is to figure out a tight grading, and the second challenge is to figure out how to cut the grading in the right places to make a real layout. And it turns out that these are two very different lithographic patterning problems. Okay. So, I go back to this graph, and real, here we’re really we’re talking about the grating itself. All these you know, rally equation and all that, it’s a very idealized case where we’re talking about printing equal lines and spaces. So we, we, we said that at 32, we went from NA lithography to this emerging lithography which is at 1.35.
And then we stayed there for 22. For 14nm, which is going to come out into the market next year, we’re going to move up to. We’re going to stay with NA ArF because there’s really nothing else on the ArF side. But we’re going to do something called pitch halving, and we’ll talk about that. And you might have encountered this as I showed some of the cartoons. You, you, I’m sure you’d have seen it in your class. so the standard way, because as you can see, these kinds of pitches, you know, the mid-twenties, it’s a pitch of 40, 40, between 40 and 50. You can’t stay on this yellow line anymore, you gotta jump up to the green line. And so that’s what we’re intending to for 14.
And then moving forward, for 10, which we have started work on right now, you know, about 6 to 8 months. We’ve started work on the 10 nanometer mode, which is going to come out in 2015. Even that’s not going to be good enough.. You know, we, we can’t be there, we’ve got to jump up there. So it’s either EUV, which is the Brown line, or the magenta line is picture quartering, and we’ll talk about that as well. So there’s different techniques to extend ArF lithography pitch halving and pitch quartering. So this is pitch halving. And the idea is you know, as the term says, you know, how do you cut your pitch in half? Right? So, a couple different ways you can do it. You know, one of them is this so-called double patterning, which is, you know, you have those bluish lines, that’s at twice the pitch you’re finally interested in getting.
You etch that into the green film. You know, whatever this, some kind of a mask. Some kind of hard mask film. then you cut some photo-resistant, create your second pattern and you interleave them. And then you transfer the composite pattern into your substrates. So, in effect you’re doing two combs at twice the picture interested in and then stick them, you know, interleave them so that you get the final pitch you want. So this is the final pitch that you desire, which is impossible to print, you know, by itself, but of course you can print twice the pitch twice and then mix them up.
you know, so that’s one approach. The other approach is a spacer based pitch division, which really turns out to be a lot more powerful and a lot more elegant way to do things. And this is really the way most, most semiconductor manufacturers do pitch division. So what you do is, again, you start with a pattern that’s twice the pitch you’re interested in, and then you deposit this conformal film, you know, that kind of goes around your original pattern.
Then you do a very directional etch, which etches perfectly vertical. So the, the, the film and the flat regions go away, leaving behind these spacers. And then you get rid of the original pattern giving you the, twice the pitch [INAUDIBLE] probably I’m sure you have seen these cartoons before. So this is pitch halving, so essentially you get half the pitch that you started off with. So it turns out that this is not that complicated to do in the fab. And there’s a lot of details, but you know, from a difficulty standpoint or even a cost standpoint, these extra process steps do add cost but not terribly so. the advantage of this method of course is you only need one lithography exposure to do this, the original pattern.
Alright. Here you need two exposures, first comb and then the second comb, and you’ve got to put them together. So this turns out to be much more expensive than that. And so, since cost is king in lithography, this technique actually is preferred by just about everybody. So the advantage of course is that you know, you get a huge boost in your pitch for essentially very little effort. Right? A relative little effort. and so your graphs, you know, the half pitch that you can do at any given numerical approach or any, for, for a given size or lens that you have, you can do essentially half of the pitch that you could otherwise. So ArF pitch division, right. You do have process complexity. You gotta figure out how to deposit these films and etch them and clean them up, and all that. But you gain significant resolution at the expense of process complexity. So that’s the trade off that you have. here are some slides showing this, you know, the, the first approach. Which is the interweave the two, two pictures approach.
So you do your first lithography, you somehow freeze the pattern. Right? So you can do a lot of different techniques. You can use bakes, you can use ion implant, you can use a lot of different ways by which you freeze the pattern. And then you come back and interleave the second pattern in between those gaps. And then you can, you know, basically develop that out, and you get your composite pattern, which you can etch, which you can then etch into your substrate. And here are some examples of you know, the so-called Litho-Freeze-Litho-Etch. There’s, there’s a litho step, and then you freeze the pattern, you put your second lithography step, and then you etch the total pattern into substrate.
Here are some examples of features that have been double patterned. And you kind of going to see it qualitatively. You’ve got these two lines that are at different height. So, this was done with your first pattern, and then you came back and put your second pattern here, and interleaved them, and then now you can transfer this thing into substrate. And you can get reasonably good lines and spaces or even contact holes, using these techniques. The spacer based pitch division is the other technique, which really is you know, turning out to be the preferred approach. so again, you start with this you know, pattern that’s you know, twice the pitch. You put the spacer around, and then you etch the spacer, so that’s what you have there.
And then you get rid of your you know, the, the pattern in between so that’s gone. These are the spacers that are left behind there, and then now you can etch that into a substrate and end up with a pitch that’s half of what you started off with. So, now you can take this technique and extend it another time. Right? So, if you take this pitch avenue you end up here. Now you put your second film on top of it and then you going to end up with a pitch which is a fourth of what you started with. So that’s kind of described in this column here. You start with that yellow pattern. [COUGH] The blue line is the first spacer. You etch the first spacer here. Get rid of that yellow thing. and then you’re left with this. You put a second spacer on top of it. Etch that, you get that and get rid of the blue and you end up with this. And so, in theory, you could do this as many times as you want. So you have pitch having, quartering, you can go to you know, 1 8th the pitch and stuff like that.
And there’s tricks. It’s like there are different flows so you can get to a sixth of the pitch you started off with. So these are tricks that you can use. You’re cheating. Really, I mean, you’re, you don’t have better lithography, but you’re able to get pitches that are quite a bit tighter than you would otherwise. [MUSIC].